Abstract: A compact D-band wideband low-noise amplifier is designed using 28-nm CMOS process. The amplifier consists of four amplifier unit, each amplifier unit employs a differential common-source structure based on the capacitive neutralization technique. The input, output, and interstage impedance matching circuits are realized by a transformer network, and the center operating frequency of each amplifier unit is centrally configured around 120 GHz and 155 GHz to implement a staggered tuning bandwidth expansion technique, which enables the amplifier to achieve a flat gain response over a wide bandwidth. Under 34mW DC power consumption, simulated and measured results show that the amplifier achieves a 19.5 dB peak gain at the center frequency of 140 GHz and a 28 GHz (128 GHz~156 GHz) 3 dB bandwidth, with a noise figure and input 1 dB compression point of 7.8 dB~9.2 dB and -19.8 dBm~-16.6 dBm, respectively. The core area of the chip is only 200 μm×550 μm.